A full-flow toolchain covering analog IC front-end design, circuit simulation, layout editing, and verification. Representative products include Aether (circuit design), ALPS (simulator), and Skipper (layout editing). Customers include leading domestic design houses and wafer fabs such as Huawei HiSilicon, SMIC, and Hua Hong Semiconductor, with a gross margin of approximately 75%.
Includes digital chip design tools covering logic synthesis, timing analysis, formal verification, and physical verification. The Darwin SoC design platform launched in 2024 delivers a complete RTL-to-GDSII flow. This business is in a rapid growth phase, primarily serving domestic AI chip and CPU/GPU design companies, with a gross margin of approximately 65%.
Provides RF/microwave circuit design and simulation tools supporting compound semiconductor processes such as GaAs and GaN, with broad applications in 5G communications and satellite communications. The representative product is RFDesigner, with customers including UNISOC and Maxscend.
Includes process development kits (iPDK), manufacturing yield analysis tools, and process model modeling services, deepening ecosystem integration with wafer fabs and supporting R&D at advanced process nodes (below 28nm). The gross margin is approximately 80%.
| Product Line | Revenue Share | Core Customers | Gross Margin |
|---|---|---|---|
| Analog Full-Flow | ~55% | Huawei HiSilicon, SMIC | ~75% |
| Digital SoC Design | ~25% | Cambricon, T-Head | ~65% |
| RF & Microwave | ~10% | UNISOC, Maxscend | ~70% |
| Wafer Manufacturing Services | ~10% | Hua Hong Semiconductor, YMTC | ~80% |
Technical Moats
Moat 1: The Most Complete Full-Flow EDA Tool Chain for Analog Circuits in China
The global EDA market is currently monopolized by three players—Synopsys, Cadence, and Siemens EDA. In China, only Empyrean Technology can provide a complete tool chain covering the entire analog circuit design flow, including design, simulation, layout, and physical verification, and it has passed process node certifications from multiple major international foundries (e.g., SMIC and Hua Hong). The completeness of this tool chain and its process adaptability constitute a significant first-mover advantage.
Moat 2: Deeply Bound Process Ecosystem and Government–Enterprise Collaboration
The company actively participates in major national projects for domestic EDA development and co-builds process design kits (iPDK) with domestic foundries, forming a joint ecosystem of "design tools + process libraries." Meanwhile, the company has received investment from the National Integrated Circuit Industry Fund (Phase II), granting it priority supply status in state-owned enterprises and the military sector, with a clear policy barrier.
Moat 3: Continuous Technology Iteration and AI Empowerment
The company embeds AI capabilities into its EDA tools, such as leveraging machine learning to accelerate simulation convergence and reinforcement learning to optimize layout placement, achieving efficiency comparable to the international top three in certain scenarios. The ALPS simulator launched in 2024 delivers performance on par with Cadence Spectre at the 5nm node.
| Dimension | Data |
|---|---|
| Global Market Share | ~1% (2023, global EDA market ~$18 billion) |
| Industry Ranking | First in China, fourth globally (behind the Big Three) |
| Major Competitors | Synopsys (~32%), Cadence (~30%), Siemens EDA (~12%) |
| Downstream Customers | HiSilicon, SMIC, HuaHong Semiconductor, YMTC, UNISOC, etc. |
| Domestic Substitution Potential | Domestic EDA market ~$2 billion; Empyrean Technology holds ~6% market share; self-sufficiency rate below 10% |
Financials and Growth
| Metric | Data (2023) |
|---|---|
| Revenue | RMB 1.45 billion |
| Gross Margin | 72.4% |
| Net Margin | 22.1% |
| R&D Investment Ratio | 45% (approx. RMB 650 million) |
| Core Growth Logic | Accelerated domestic substitution (EDA independent-and-controllable policy), product line expansion into digital and RF, and tool demand driven by wafer fab process node upgrades |
The three-year revenue CAGR is approximately 35%. In H1 2024, revenue reached RMB 920 million, up 48% year-over-year. The company's primary growth drivers are the increased willingness of the domestic semiconductor supply chain to procure domestic EDA tools, as well as tool demand stemming from the rising complexity of AI chip design.
Key Risks:
Intensifying International Competition: Leveraging their technological advantages and ecosystem barriers, Synopsys and Cadence may suppress Empyrean Technology's growth space in the high-end segment.
Technology Breakthroughs Below Expectations: The digital SoC full-flow toolchain still lags international giants by 2–3 generations, making it difficult to achieve true substitution in advanced process nodes (below 7nm).
Customer Concentration Risk: Revenue from the top five customers accounts for over 50% of total revenue. If major customers switch toolchains or develop in-house EDA tools, the company's performance could be significantly impacted.
High Valuation and Lock-up Expiry Pressure: Since its IPO, the dynamic P/E ratio has consistently remained above 200x. Market sentiment fluctuations could lead to significant stock price corrections.
Core Investment Thesis / Industry Value Summary: