Moat 1: Breaking the Physical Limit of Lithography — CoWoS Advanced Packaging
The Reticle Limit of lithography (maximum exposure field of approximately 26×33mm) defines the theoretical upper bound of a single chip. TSMC's CoWoS technology rewires multiple functional chips (e.g., GPU, HBM, SerDes) through a silicon interposer, allowing the total system-level package area to far exceed a single lithography field, thereby circumventing the Reticle Limit. The current CoWoS-S (with silicon interposer) and CoWoS-L (with local interconnect) versions have evolved to the fifth generation, enabling integration of up to 8 HBM3e stacks and providing over 2TB/s of memory bandwidth.
Moat 2: Ecosystem Lock-in Through Leading Process Nodes
TSMC is the only pure-play foundry capable of stable high-volume production at N5/N3 with leading yields. Once a customer completes tape-out, migration costs are extremely high (design IP, process libraries, and EDA tools are deeply integrated). TSMC also offers DTCO (Design-Technology Co-Optimization), working closely with NVIDIA and AMD to further strengthen customer stickiness. In addition, TSMC operates the world's largest fleet of EUV lithography machines (over 100 units), forming a physical capacity barrier.
| Dimension | Data |
|---|---|
| Global wafer foundry market share | ~60% (2024, TrendForce) |
| Advanced process (7nm and below) share | ~90% |
| CoWoS advanced packaging market share | ~90%+ (exclusive supplier to NVIDIA and AMD) |
| Industry ranking | #1 globally in wafer foundry |
| Key competitors | Samsung Electronics (3nm GAA imitation), Intel (IFS foundry) |
| Downstream customers | NVIDIA (~15% revenue), AMD, Apple (~25%), Qualcomm, MediaTek |
Financials and Growth
| Metric | Data |
|---|---|
| Revenue (2024) | ~$78 billion |
| Gross margin | ~53% (2024 Q4) |
| Net margin | ~38% |
| Core growth drivers | 1) Surging AI chip demand; NVIDIA/AMD continuously ramp CoWoS orders; 2) Smartphone and PC migration to 3nm; 3) Intel's foundry efforts unlikely to challenge TSMC's position in the near term |
Growth Drivers: CoWoS capacity is expected to increase by more than 50% in 2025, and N2 (2nm) is scheduled for volume production in 2025, adopting nanosheet transistors to further consolidate TSMC's technology leadership.
Key Risks:
- Geopolitical risk: Cross-strait tensions could disrupt the global semiconductor supply chain if conflict escalates. US/Japan government initiatives promoting chip localization (e.g., TSMC Arizona fab, Kumamoto fab in Japan) increase operational complexity and costs.
- Technology iteration risk: Samsung has already begun volume production of 3nm GAA, and Intel IFS could potentially capture some high-end customers if it achieves a breakthrough on the 18A node.
- Capacity expansion risk: CoWoS capacity expansion requires a long lead time (approximately 12-18 months). If AI demand exceeds expectations, this may continue to bottleneck NVIDIA shipments, potentially damaging TSMC's reputation.
Core Investment Thesis / Industry Value Summary:
TSMC is the core physical foundation of the AI computing boom. Through CoWoS technology, it has perfectly solved the chip scaling challenge imposed by the lithography physical limit (Reticle Limit), firmly controlling the vertical capability from 3nm process nodes to advanced packaging. In the near term, the CoWoS capacity bottleneck is a pain point; in the long term, however, it is a moat — customers cannot bypass TSMC to achieve volume shipments. Over the next 3-5 years, TSMC will maintain its monopolistic position in AI chip manufacturing and packaging, representing the highest-certainty value node in the AI industry chain.